1. Field of the Invention
The present invention relates to a method and a channel apparatus for rearranging received read data in order of generation of addresses, which are used with a split bus control system in which, at a time of memory read, transmission of memory read request information containing a memory address and a source identifier designating a requesting source and transmission of response information containing read data and a destination identifier corresponding to the source identifier are carried out separately.
2. Description of the Related Art
With a conventional data processing system for the so-called split bus control system, a main storage device is directly connected to a high-speed input/output device, such as a magnetic disk unit, and is connected through a channel apparatus to a clock synchronous system bus. The main storage device comprises a memory control unit and a plurality of memory banks, and the memory control unit generally allows interleaved operation of the memory banks for improved performance. Data is transmitted between the input/output device and the main storage device via the channel unit in data block or word units and memory addresses used for accessing the main storage device are updated in ascending order. In the split bus control system, in a memory read mode, the transmission of memory read request information from the input/output device and the transmission of response information from the main memory for the request information are separated from each other. That is, the request information and the response information are not consecutive. The memory read request information includes a memory address and a source identifier SID designating a request source. The response information includes read data and a destination identifier DID designating the destination of the corresponding response. As the DID of the response information the SID of the corresponding memory read request information is used. The read data contained in the response information will be entered into a channel unit to which the same SID as the DID is assigned.
In a conventional data processing system as described above, there is a need for an improvement in data transmission rate. As a measure to increase the data transmission rate, after the issue of memory read request information from a channel unit to the main storage device the next memory read request information could be issued before the return of response information containing read data for the previous request. However, since the memory control device of the main memory device first processes memory read request information addressed to a memory bank which is not busy, there is no assurance that responses are returned in the order of generation of request information, depending upon the states of the memory banks. Hence, where read data in the response information returned from the memory control device are stored in sequence in a data buffer, the arrangement of the read data may often be out of order of generation of the memory read request information. For this reason, the memory read request information cannot thus be issued consecutively and, as a result, the memory read operation cannot be sped.